Pivot3 Blog

NVMe Technology Primer

Part 1 in a 3-part Series on NVMe technology and how Pivot3 uses NVMe to get the most out hyperconverged

Flash memory technology has been around for a long time. Mainstream adoption (consumer and enterprise) has occurred in the last five years in the form of Solid State Disk (SSD) drives connected into the same disk interfaces (SAS/SATA) that have been used for decades for spinning Hard Disk Drives (HDD). While this initial implementation of flash memory as SSD has gained broad adoption, it is widely recognized by the industry that connecting flash memory via a legacy disk controller architecture has major limitations for both performance and management.

In order to address these issues, architectural and datapath changes needed to occur. The most popular approach was to connect the flash memory via the PCIe bus in order to get the most optimized performance datapath. Early implementations of PCIe-connected flash were proprietary in that flash vendors had to provide the complete stack (software, firmware, mgmt. tools, etc) for plugging PCIe flash into a system. Fusion-IO (Sandisk/Western Digital) was one of the pioneers of this approach and garnered a lot of early adopter customer success.

While many of the proprietary implementations of PCIe flash were successful, as with many industry trends a standard approach was needed for widespread adoption. This is where NVMe comes onto the scene. The Non-volatile Memory Express (NVMe) working group is a standards group in the flash memory/storage industry whereby the goal was to create a standard way of integrating PCIe flash into systems for interfaces, software and management. As a result of this working group, the support for NVMe connected flash has reached mainstream. Nearly every flash device supplier on the planet now has NVMe connected flash devices available. Likewise, consumer and enterprise products and systems now include NVMe connected flash support.

There are two fundamental requirements for a system to support NVMe:

  1. The system must be able to support a PCIe connected flash datapath, and
  2. The system must include the required NVMe software (device driver and mgmt. tools) to allow the operating system to communicate with the NVMe device(s).

Finally, in order to take advantage of the full benefits of NVMe-enabled devices, the higher-level systems and software should be modified (re-architected and/or re-written) to address NVMe connected flash storage natively and not treat flash as simply a different form of a disk drive.

As I mentioned previously, the promise of NVMe is beginning to become mainstream with more and more vendors and products embracing this new technology. The benefits for customers are three-fold:

  • Better application performance: NVMe devices can service IO at much lower latencies than previous generations of SSD (up to 10X lower) and HDD (up to 1000X lower). This translates into better application response time which can be measured by better end-user experience, more transactions processed and lower wait times for customers.
  • Lower costs: By packing more performance into the same footprint with NVMe, customers can reduce the infrastructure required to meet their performance needs. Less infrastructure means lower capex acquisition costs and lower opex for power, cooling, data center footprint costs.
  • More efficient use of resources: Most IT systems today are shared resource pools. Virtualization technologies have allowed customers to achieve high levels of consolidation for both compute and storage resources. By providing a more efficient IO datapath, NVMe has the added benefit that the systems spend less time waiting for IO to complete and are therefore more efficient with using their resources. These resources can then be leveraged to do even more work.

With the introduction of the Acuity HCI products earlier this year, Pivot3 is fully engaged in leading the NVMe datapath transition for our customers. Stay tuned for more NVMe-related posts on Why NVMe Matters for HCI and Pivot3 NVMe Architecture and Implementation.